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1 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation ultra fast 40mbps differential transmission rates available improved esd tolerance for analog i/os with 15kv hbm. internal transceiver termination resistors for v.11 and v.35 interface modes: ? rs-232 (v.28) ? eia-530 (v.10 & v.11) ? x.21 (v.11) ? eia-530a (v.10 & v.11) ? rs-449/v.36 ? v.35 (v.10 & v.11) protocols are software selectable with 3-bit word eight (8) drivers and eight (8) receivers v.35 and v.11 receiver termination network disable option internal line or digital loopback for diagnostic testing adheres to net1/net2 and tbr-2 compliancy requirements easy flow-through pinout +5v only operation individual driver and receiver enable/disable controls operates in either dte or dce mode SP509 rugged 40mbps, 8 channel multi-protocol transceiver with programmable dce/dte and termination resistors description the SP509 is a monolithic device that supports eight (8) popular serial interface standards for wide area network (wan) connectivity. the SP509 is fabricated using a low power bicmos process technology, and incorporates a sipex regulated charge pump allowing +5v only operation. sipex's patented charge pump provides a regulated output of + 5.8v, which will provide enough voltage for compliant operation in all modes. eight (8) drivers and eight (8) receivers can be configured via software for any of the above interface modes at any time. the SP509 requires no additional external components for compliant operation for all of the eight (8) modes of operation other than four capacitors used for the internal charge pump. all necessary termination is integrated within the SP509 and is switchable when v.35 drivers and v.35 receivers, or when v.11 receivers are used. the SP509 provides the controls and transceiver availability for operating as either a dte or dce. additional features with the SP509 include internal loopback that can be initiated in any of the operating modes by use of the loopback pin. while in loopback mode, receiver outputs are internally connected to driver inputs creating an internal signal path bypassing the serial communications controller for diagnostic testing. the SP509 also includes a latch enable pin with the driver and receiver address decoder. the internal v.11 or v.35 receiver termination can be switched off using a control pin (term_off) for monitoring applications. all eight (8) drivers and receivers in the SP509 include separate enable pins for added convenience. the SP509 is ideal for wan serial ports in networking equipment such as routers, concentrators, network muxes, dsu/csu's, networking test equipment, and other access devices. applicable u.s. patents-5,306,954; and others patents pending ? applications router frame relay csu dsu pbx secure communication terminals features now available in lead free packaging refer to page 7 for pinout
2 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation t a = +25 c and v cc = +4.75v to +5.25v unless otherwise noted. min. typ. max. units conditions logic inputs v il 0.8 volts v ih 2.0 volts logic outputs v ol 0.4 volts i out = ?3.2ma v oh 2.4 volts i out = 1.0ma v.28 driver dc parameters outputs open circuit voltage 15 volts per figure 1 loaded voltage 5.0 15 volts per figure 2 short-circuit current 100 ma per figure 4, v out =0v power-off impedance 300 ? per figure 5 ac parameters v cc = +5v for ac parameters outputs transition time 1.5 s per figure 6 ; +3v to -3v instantaneous slew rate 30 v/ s per figure 3 propagation delay t phl 0.5 1 5 s t plh 0.5 1 5 s max.transmission rate 120 230 kbps v.28 receiver dc parameters inputs input impedance 3 7 k ? per figure 7 open-circuit bias +2.0 volts per figure 8 high threshold 1.7 3.0 volts low threshold 0.8 1.2 volts ac parameters v cc = +5v for ac parameters propagation delay t phl 50 100 500 ns t plh 50 100 500 ns absolute maximum ratings these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. v cc ................................................................................................ +7v input voltages: logic ................................................ -0.3v to (v cc +0.5v) drivers ............................................. -0.3v to (v cc +0.5v) receivers ........................................................... 15.5v output voltages: logic ................................................ -0.3v to (v cc +0.5v) drivers ................................................................... 12v receivers ........................................ -0.3v to (v cc +0.5v) storage temperature ................................................ -65 c to +150 c power dissipation ................................................................. 1520mw (derate 19.0mw/ c above +70 c) package derating: ? ja ................................................................................................................. 52.7 c/w ? jc .................................................................................................................... 6.5 c/w storage considerations due to the relatively large package size of the 100-pin quad flat- pack, storage in a low humidity environment is preferred. large high density plastic packages are moisture sensitive and should be stored in dry vapor barrier bags. prior to usage, the parts should remain bagged and stored below 40 c and 60%rh. if the parts are removed from the bag, they should be used within 48 hours or stored in an environment at or below 20%rh. if the above conditions cannot be followed, the parts should be baked for four hours at 125 c in order to remove moisture prior to soldering. sipex ships the 100-pin lqfp in dry vapor barrier bags with a humidity indicator card and desiccant pack. the humidity indicator should be below 30%rh. electrical specifications
3 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation t a = +25 c and v cc = +4.75v to +5.25v unless otherwise noted. min. typ. max. units conditions v.28 receiver (continued) ac parameters (cont.) max.transmission rate 120 235 kbps v.10 driver dc parameters outputs open circuit voltage 4.0 6.0 volts per figure 9 test-terminated voltage 0.9v oc volts per figure 10 short-circuit current 150 ma per figure 11 power-off current 100 a per figure 12 ac parameters v cc = +5v for ac parameters outputs transition time 200 ns per figure 13 ; 10% to 90% propagation delay t phl 30 100 500 ns t plh 30 100 500 ns max.transmission rate 120 kbps v.10 receiver dc parameters inputs input current ?3.25 +3.25 ma per figures 14 and 15 input impedance 4 k ? sensitivity 0.3 volts ac parameters v cc = +5v for ac parameters propagation delay t phl 50 ns t plh 50 ns max.transmission rate 120 kbps v.11 driver dc parameters outputs open circuit voltage 6.0 volts per figure 16 test terminated voltage 2.0 volts per figure 17 0.5v oc 0.67v oc volts balance 0.4 volts per figure 17 offset +3.0 volts per figure 17 short-circuit current 150 ma per figure 18 power-off current 100 a per figure 19 ac parameters v cc = +5v for ac parameters outputs transition time 10 ns per figures 21 and 36 ; 10% to 90% propagation delay using c l = 50pf; t phl 30 50 ns per figures 33 and 36 t plh 30 50 ns per figures 33 and 36 differential skew 2 5 ns per figures 33 and 36 (|t phl - t plh |) max.transmission rate 40 mbps channel to channel skew 2 ns v.11 receiver dc parameters inputs common mode range ?7 +7 volts sensitivity 0.2 volts electrical specifications
4 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation t a = +25 c and v cc = +4.75v to +5.25v unless otherwise noted. min. typ. max. units conditions v.11 receiver (continued) dc parameters (cont.) input current ?3.25 3.25 ma per figure 20 and 22 ; power on or off current w/100 ? termination 60.75 ma per figure 23 and 24 input impedance 4 k ? ac parameters v cc = +5v for ac parameters propagation delay using c l = 50pf; t phl 30 50 ns per figures 33 and 38 t plh 30 50 ns per figures 33 and 38 skew (|t phl - t plh |) 2 5 ns per figure 33 max.transmission rate 40 mbps channel to channel skew 2 ns v.35 driver dc parameters outputs test terminated voltage 0.44 0.66 volts per figure 25 offset 0.6 volts per figure 25 output overshoot -0.2v st +0.2v st volts per figure 25 ; v st = steady state value source impedance 50 150 ? per figure 27 ; z s = v 2 /v 1 x 50 short-circuit impedance 135 165 ? per figure 28 ac parameters v cc = +5v for ac parameters outputs transition time 7 20 ns per figure 29 ; 10% to 90% propagation delay t phl 30 50 ns per figures 33 and 36 ; c l = 20pf t plh 30 50 ns per figures 33 and 36 ; c l = 20pf differential skew 2 5 ns per figures 33 and 36 ; c l = 20pf (|t phl - t plh |) max.transmission rate 40 mbps channel to channel skew 2 ns v.35 receiver dc parameters inputs sensitivity 50 +100 mv source impedance 90 110 ? per figure 30 ; z s = v 2 /v 1 x 50 ? short-circuit impedance 135 165 ? per figure 31 ac parameters v cc = +5v for ac parameters propagation delay t phl 30 50 ns per figures 33 and 38 ; c l = 20pf t plh 30 50 ns per figures 33 and 38 ; c l = 20pf skew (|t phl - t plh |) 2 5 ns per figure 33 ; c l = 20pf max.transmission rate 40 mbps channel to channel skew 2 ns transceiver leakage current driver output 3-state current 500 a per figure 32 ; drivers disabled rcvr output 3-state current 1 10 at x & r x disabled, 0.4v - v o - 2.4v power requirements v cc 4.75 5.00 5.25 volts i cc (shutdown mode) 1 a all i cc values are with v cc = +5v (v.28/rs-232) 95 ma f in = 120kbps; drivers active & loaded (v.11/rs-422) 230 ma f in = 10mbps; drivers active & loaded (eia-530 & rs-449) 270 ma f in = 10mbps; drivers active & loaded (v.35) 170 ma v.35 @ f in = 10mbps, v.28 @ 20kbps (eia-530a) 200 ma f in = 10mbps; drivers active & loaded electrical specifications
5 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation t a = +25 c and v cc = +5.0v unless otherwise noted. parameter min. typ. max. units conditions driver delay time between active mode and tri-state mode rs-232/v.28 t pzl ; tri-state to output low 0.11 5.0 sc l = 100pf, fig. 34 & 40 ; s 2 closed t pzh ; tri-state to output high 0.11 2.0 sc l = 100pf, fig. 34 & 40 ; s 2 closed t plz ; output low to tri-state 0.05 2.0 sc l = 100pf, fig. 34 & 40 ; s 2 closed t phz ; output high to tri-state 0.05 2.0 sc l = 100pf, fig. 34 & 40 ; s 2 closed rs-423/v.10 t pzl ; tri-state to output low 0.07 2.0 sc l = 100pf, fig. 34 & 40 ; s 2 closed t pzh ; tri-state to output high 0.05 2.0 sc l = 100pf, fig. 34 & 40 ; s 2 closed t plz ; output low to tri-state 0.55 2.0 sc l = 100pf, fig. 34 & 40 ; s 2 closed t phz ; output high to tri-state 0.12 2.0 sc l = 100pf, fig. 34 & 40 ; s 2 closed rs-422/v.11 t pzl ; tri-state to output low 0.04 10.0 sc l = 100pf, fig. 34 & 37 ; s 1 closed t pzh ; tri-state to output high 0.05 2.0 sc l = 100pf, fig. 34 & 37 ; s 2 closed t plz ; output low to tri-state 0.03 2.0 sc l = 15pf, fig. 34 & 37 ; s 1 closed t phz ; output high to tri-state 0.11 2.0 sc l = 15pf, fig. 34 & 37 ; s 2 closed v.35 t pzl ; tri-state to output low 0.85 10.0 sc l = 100pf, fig. 34 & 37 ; s 1 closed t pzh ; tri-state to output high 0.36 2.0 sc l = 100pf, fig. 34 & 37 ; s 2 closed t plz ; output low to tri-state 0.06 2.0 sc l = 15pf, fig. 34 & 37 ; s 1 closed t phz ; output high to tri-state 0.05 2.0 sc l = 15pf, fig. 34 & 37 ; s 2 closed receiver delay time between active mode and tri-state mode rs-232/v.28 t pzl ; tri-state to output low 0.05 2.0 sc l = 100pf, fig. 35 & 40 ; s 1 closed t pzh ; tri-state to output high 0.05 2.0 sc l = 100pf, fig. 35 & 40 ; s 2 closed t plz ; output low to tri-state 0.65 2.0 sc l = 100pf, fig. 35 & 40 ; s 1 closed t phz ; output high to tri-state 0.65 2.0 sc l = 100pf, fig. 35 & 40 ; s 2 closed rs-423/v.10 t pzl ; tri-state to output low 0.04 2.0 sc l = 100pf, fig. 35 & 40 ; s 1 closed t pzh ; tri-state to output high 0.03 2.0 sc l = 100pf, fig. 35 & 40 ; s 2 closed t plz ; output low to tri-state 0.03 2.0 sc l = 100pf, fig. 35 & 40 ; s 1 closed t phz ; output high to tri-state 0.03 2.0 sc l = 100pf, fig. 35 & 40 ; s 2 closed other ac characteristics
6 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation t a = +25 c and v cc = +5.0v unless otherwise noted. parameter min. typ. max. units conditions rs-422/v.11 t pzl ; tri-state to output low 0.04 2.0 sc l = 100pf, fig. 35 & 39 ; s 1 closed t pzh ; tri-state to output high 0.03 2.0 sc l = 100pf, fig. 35 & 39 ; s 2 closed t plz ; output low to tri-state 0.03 2.0 sc l = 15pf, fig. 35 & 39 ; s 1 closed t phz ; output high to tri-state 0.03 2.0 sc l = 15pf, fig. 35 & 39 ; s 2 closed v.35 t pzl ; tri-state to output low 0.04 2.0 sc l = 100pf, fig. 35 & 39 ; s 1 closed t pzh ; tri-state to output high 0.03 2.0 sc l = 100pf, fig. 35 & 39 ; s 2 closed t plz ; output low to tri-state 0.03 2.0 sc l = 15pf, fig. 35 & 39 ; s 1 closed t phz ; output high to tri-state 0.03 2.0 sc l = 15pf, fig. 35 & 39 ; s 2 closed transceiver to transceiver skew (per figures 32, 33, 36, 38) rs-232 driver 100 ns [ (t phl ) tx1 ? (t phl ) txn ] 100 ns [ (t plh ) tx1 ? (t plh ) txn ] rs-232 receiver 20 ns [ (t phl ) rx1 ? (t phl ) rxn ] 20 ns [ (t phl ) rx1 ? (t phl ) rxn ] rs-422 driver 2 ns [ (t phl ) tx1 ? (t phl ) txn ] 2ns[ (t plh ) tx1 ? (t plh ) txn ] rs-422 receiver 2 ns [ (t phl ) rx1 ? (t phl ) rxn ] 3ns[ (t phl ) rx1 ? (t phl ) rxn ] rs-423 driver 5 ns [ (t phl ) tx2 ? (t phl ) txn ] 5ns[ (t plh ) tx2 ? (t plh ) txn ] rs-423 receiver 5 ns [ (t phl ) rx2 ? (t phl ) rxn ] 5ns[ (t phl ) rx2 ? (t phl ) rxn ] v.35 driver 2 ns [ (t phl ) tx1 ? (t phl ) txn ] 2ns[ (t plh ) tx1 ? (t plh ) txn ] v.35 receiver 2 ns [ (t phl ) rx1 ? (t phl ) rxn ] 2ns[ (t phl ) rx1 ? (t phl ) rxn ] other ac characteristics (continued)
7 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation vcc 1 gnd 2 sden 3 tten 4 sten 5 rsen 6 tren 7 rrcen 8 rlen 9 llen 10 rden 11 r ten 12 txcen 13 csen 14 dmen 15 rrten 16 icen 17 tmen 18 d0 19 d1 20 d2 21 term_off 22 d_latch 23 n/c 24 gnd 25 vcc 26 loopback 27 txd 28 txce 29 st 30 r ts 31 dtr 32 dcd_dce 33 rl 34 ll 35 rxd 36 rxc 37 txc 38 cts 39 dsr 40 dcd_dte 41 ri 42 tm 43 gnd 44 vcc 45 v35rgnd 46 rd(b) 47 rd(a) 48 r t(b) 49 r t(a) 50 75 tr(a) 74 gnd 73 vdd 72 c1+ 71 vcc 70 c2+ 69 c1- 68 gnd 67 c2- 66 vss 65 rl(a) 64 vcc 63 ll(a) 62 tm(a) 61 ic(a) 60 rrt(a) 59 rrt(b) 58 v10gnd 57 dm(a) 56 dm(b) 55 cs(a) 54 cs(b) 53 txc(a) 52 gnd 51 txc(b) 100 sd(b) 99 v35tgnd1 98 vcc 97 sd(a) 96 gnd 95 tt(b) 94 v35tgnd2 93 vcc 92 tt(a) 91 gnd 90 st(b) 89 v35tgnd3 88 vcc 87 st(a) 86 gnd 85 rs(b) 84 vcc 83 rs(a) 82 gnd 81 rrc(a) 80 vcc 79 rrc(b) 78 tr(b) 77 vcc 76 n/c SP509 ? pinout 100 pin lqfp
8 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation pin number pin name description pin number pin name description 1 vcc 5v power supply input 51 txc(b) txc non-inverting input 2 gnd signal ground 52 gnd signal ground 3 sden txd driver enable input 53 txc(a) txc inverting input 4 tten txce driver enable input 54 cs(b) cts non-inverting input 5 sten st driver enable input 55 cs(a) cts inverting input 6 rsen rts driver enable input 56 dm(b) dsr non-inverting input 7 tren dtr driver enable input 57 dm(a) dsr inverting input 8 rrcen dcd driver enable input 58 gndv10 v.10 rx reference node 9 rlen rl driver enable input 59 rrt(b) dcd dte non-inverting input 10 llen# ll driver enable input 60 rrt(a) dcd dte inverting input 11 rden# rxd receiver enable input 61 ic ri receiver input 12 rten# rxc receiver enable input 62 tm(a) tm receiver input 13 txcen# txc receiver enable input 63 ll(a) ll driver output 14 csen# cts receiver enable input 64 vcc power supply input 15 dmen# dsr receiver enable input 65 rl(a) rl driver output 16 rrten# dcd dte receiver enable input 66 vss1 -2xvcc charge pump output 17 icen# ri receiver enable input 67 c2n charge pump capacitor 18 tmen tm receiver enable input 68 gnd signal ground 19 d0 mode select input 69 c1n charge pump capacitor 20 d1 mode select input 70 c2p charge pump capacitor 21 d2 mode select input 71 vcc power supply input 22 term_off termination disable input 72 c1p charge pump capacitor 23 d_latch# decoder latch input 73 vdd 2xvcc charge pump output 24 nc no connect 74 gnd signal ground 25 gnd signal ground 75 tr(a) dtr inverting output 26 vcc 5v power supply input 76 nc no connect 27 loopback# loopback mode enable input 77 vcc power supply input 28 txd txd driver ttl input 78 tr(b) dtr non-inverting output 29 txce txce driver ttl input 79 rrc(b) dcd non-inverting output 30 st st driver ttl input 80 vcc power supply input 31 rts rts driver ttl input 81 rrc(a) dcd inverting output 32 dtr dtr driver ttl input 82 gnd signal ground 33 dcd_dce dcd dce driver ttl input 83 rs(a) rts inverting output 34 rl rl driver ttl input 84 vcc power supply input 35 ll ll driver ttl input 85 rs(b) rts non-inverting output 36 rxd rxd receiver ttl output 86 gnd signal ground 37 rxc rxc receiver ttloutput 87 st(a) st inverting output 38 txc txc receiver ttl output 88 vcc power supply input 39 cts cts receiver ttl output 89 v35tgnd3 st termination referance 40 dsr dsr receiver ttl output 90 st(b) st non-inverting output 41 dcd_dte dcd dte receiver ttl output 91 gnd signal ground 42 ri ri receiver ttl output 92 tt(a) txce inverting output 43 tm tm receiver ttl output 93 vcc 5v power supply input 44 gnd signal ground 94 v35tgnd2 st termination referance 45 vcc power supply input 95 tt(b) txce non-inverting output 46 v35rgnd reciever termination refrence 96 gnd signal ground 47 rd(b) rxd non-inverting input 97 sd(a) txd inverting output 48 rd(a) rxd inverting input 98 vcc 5v power supply input 49 rt(b) rxc non-inverting input 99 v35tgnd1 st termination referance 50 rt(a) rxc inverting input 100 sd(b) txd non-inverting output pin description
9 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation table 1. driver mode selection table 2. receiver mode selection SP509 driver table SP509 receiver table t u p t u o r e v i r d n i p e d o m 5 3 . v 0 3 5 - a i e e d o m 2 3 2 - s r e d o m ) 8 2 . v ( a 0 3 5 - a i e e d o m 9 4 4 - s r e d o m ) 6 3 . v ( e d o m 1 2 . x ) 1 1 . v ( n w o d t u h s d e t s e g g u s l a n g i s e d o m ) 2 d , 1 d , 0 d ( 1 0 00 1 01 1 00 0 11 0 10 1 11 1 1 t 1 ) a ( t u o5 3 . v1 1 . v8 2 . v1 1 . v1 1 . v1 1 . vz - h g i h) a ( d x t t 1 ) b ( t u o5 3 . v1 1 . vz - h g i h1 1 . v1 1 . v1 1 . vz - h g i h) b ( d x t t 2 ) a ( t u o5 3 . v1 1 . v8 2 . v1 1 . v1 1 . v1 1 . vz - h g i h) a ( e c x t t 2 ) b ( t u o5 3 . v1 1 . vz - h g i h1 1 . v1 1 . v1 1 . vz - h g i h) b ( e c x t t 3 ) a ( t u o5 3 . v1 1 . v8 2 . v1 1 . v1 1 . v1 1 . vz - h g i h) a ( e c d _ c x t t 3 ) b ( t u o5 3 . v1 1 . vz - h g i h1 1 . v1 1 . v1 1 . vz - h g i h) b ( e c d _ c x t t 4 ) a ( t u o8 2 . v1 1 . v8 2 . v1 1 . v1 1 . v1 1 . vz - h g i h) a ( s t r t 4 ) b ( t u oz - h g i h1 1 . vz - h g i h1 1 . v1 1 . v1 1 . vz - h g i h) b ( s t r t 5 ) a ( t u o8 2 . v1 1 . v8 2 . v0 1 . v1 1 . v1 1 . vz - h g i h) a ( r t d t 5 ) b ( t u oz - h g i h1 1 . vz - h g i hz - h g i h1 1 . v1 1 . vz - h g i h) b ( r t d t 6 ) a ( t u o8 2 . v1 1 . v8 2 . v1 1 . v1 1 . v1 1 . vz - h g i h) a ( e c d _ d c d t 6 ) b ( t u oz - h g i h1 1 . vz - h g i h1 1 . v1 1 . v1 1 . vz - h g i h) b ( e c d _ d c d t 7 ) a ( t u o8 2 . v0 1 . v8 2 . v0 1 . v0 1 . vz - h g i hz - h g i hl r t 8 ) a ( t u o8 2 . v0 1 . v8 2 . v0 1 . v0 1 . vz - h g i hz - h g i hl l t u p n i r e v i e c e r n i p e d o m 5 3 . v 0 3 5 - a i e e d o m 2 3 2 - s r e d o m ) 8 2 . v ( a 0 3 5 - a i e e d o m 9 4 4 - s r e d o m ) 6 3 . v ( e d o m 1 2 . x ) 1 1 . v ( n w o d t u h s d e t s e g g u s l a n g i s e d o m ) 2 d , 1 d , 0 d ( 1 0 00 1 01 1 00 0 11 0 10 1 11 1 1 r 1 ) a ( n i5 3 . v1 1 . v8 2 . v1 1 . v1 1 . v1 1 . vz - h g i h) a ( d x r r 1 ) b ( n i5 3 . v1 1 . vz - h g i h1 1 . v1 1 . v1 1 . vz - h g i h) b ( d x r r 2 ) a ( n i5 3 . v1 1 . v8 2 . v1 1 . v1 1 . v1 1 . vz - h g i h) a ( c x r r 2 ) b ( n i5 3 . v1 1 . vz - h g i h1 1 . v1 1 . v1 1 . vz - h g i h) b ( c x r r 3 ) a ( n i5 3 . v1 1 . v8 2 . v1 1 . v1 1 . v1 1 . vz - h g i h) a ( e t d _ c x t r 3 ) b ( n i5 3 . v1 1 . vz - h g i h1 1 . v1 1 . v1 1 . vz - h g i h) b ( e t d _ c x t r 4 ) a ( n i8 2 . v1 1 . v8 2 . v1 1 . v1 1 . v1 1 . vz - h g i h) a ( s t c r 4 ) b ( n iz - h g i h1 1 . vz - h g i h1 1 . v1 1 . v1 1 . vz - h g i h) b ( s t c r 5 ) a ( n i8 2 . v1 1 . v8 2 . v0 1 . v1 1 . v1 1 . vz - h g i h) a ( r s d r 5 ) b ( n iz - h g i h1 1 . vz - h g i hz - h g i h1 1 . v1 1 . vz - h g i h) b ( r s d r 6 ) a ( n i8 2 . v1 1 . v8 2 . v1 1 . v1 1 . v1 1 . vz - h g i h) a ( e t d _ d c d r 6 ) b ( n iz - h g i h1 1 . vz - h g i h1 1 . v1 1 . v1 1 . vz - h g i h) b ( e t d _ d c d r 7 ) a ( n i8 2 . v0 1 . v8 2 . v0 1 . v0 1 . vz - h g i hz - h g i hi r r 8 ) a ( n i8 2 . v0 1 . v8 2 . v0 1 . v0 1 . vz - h g i hz - h g i hm t
10 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation figure 1. v.28 driver output open circuit voltage figure 2. v.28 driver output loaded voltage figure 3. v.28 driver output slew rate figure 4. v.28 driver output short-circuit current figure 6. v.28 driver output rise/fall times figure 5. v.28 driver output power-off impedance test circuits a v oc c a v t c 3k ? a v t c 7k ? oscilloscope scope used for slew rate measurement. a i sc c a c v cc = 0v 2v i x a c 3k ? 2500pf oscilloscope
11 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation figure 7. v.28 receiver input impedance figure 8. v.28 receiver input open circuit bias figure 9. v.10 driver output open-circuit voltage figure 10. v.10 driver output test terminated voltage figure 12. v.10 driver output power-off current figure 11. v.10 driver output short-circuit current a c i ia 15v a c v oc a v oc 3.9k ? c a v t 450 ? c a i sc c a c 0.25v v cc = 0v i x
12 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation figure 13. v.10 driver output transition time figure 14. v.10 receiver input current figure 15. v.10 receiver input iv graph figure 16. v.11 driver output open-circuit voltage figure 17. v.11 driver output test terminated voltage figure 18. v.11 driver output short-circuit current a 450 ? c oscilloscope a c i ia 10v v .10 receiver +3.25ma -3.25ma +3v +10v -3v -10v maximum input current vesus voltage a b v oc 3.9k ? v oca v ocb c a b v t 50 ? v os c 50 ? a b c i sa i sb
13 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation figure 19. v.11 driver output power-off current figure 20. v.11 receiver input current figure 21. v.11 driver output rise/fall time figure 22. v.11 receiver input iv graph a b c i xa 0.25v a b c i xb 0.25v v cc = 0v v cc = 0v a b c i ia 10v c i ib 10v a b a b 50 ? c 50 ? 50 ? v e oscilloscope v. 11 receiver +3.25ma -3.25ma +3v +10v -3v -10v maximum input current vesus voltage
14 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation figure 23. v.11 receiver input current w/ termination figure 24. v.11 receiver input graph w/ termination figure 25. v.35 driver output test terminated voltage figure 26. v.35 driver output offset voltage figure 27. v.35 driver output source impedance a b c i ia 6v c i ib 6v a b 100 ? to 150 ? 100 ? to 150 ? v. 11 receiver w/ optional cable termination (100 ? to 150 ? ) i [ma] = v [v] / 0.1 i [ma] = v [v] - 3) / 4.0 i [ma] = v [v] / 0.1 i [ma] = v [v] - 3) / 4.0 -6v -3v +3v +6v maximum input current versus voltage a b 50 ? c 50 ? v t v os a b 50 ? c 50 ? v t v os a b v 2 50 ? c 24khz, 550mv p-p sine wave v 1
15 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation figure 32. driver output leakage current test figure 33. driver/receiver timing test circuit figure 30. v.35 receiver input source impedance figure 29. v.35 driver output rise/fall time figure 31. v.35 receiver input short-circuit impedance figure 28. v.35 driver output short-circuit impedance a b c i sc 2v a b c 50 ? oscilloscope 50 ? 50 ? a b v 2 50 ? c 24khz, 550mv p-p sine wave v 1 a b c i sc 2v a b i zsc logic ?1? 12v 11 1 d 2 d 1 d 0 v cc = 0v v cc any one of the three conditions for disabling the driver. c l1 15pf r out b a b a t in c l2 f in (50% duty cycle, 2.5v p-p )
16 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation figure 34. driver timing test load circuit figure 35. receiver timing test load circuit figure 36. driver propagation delays figure 37. driver enable and disable times figure 38. receiver propagation delays 500 ? c l output under t est s 1 s 2 v cc 1k ? 1k ? c rl receiver output s 1 s 2 t est point v cc +3v 0v driver input a b driver output v o + differential output v b ? v a 0v v o ? 1.5v 1.5v t plh t r t f f > 10mhz; t r < 10ns; t f < 10ns v o 1/2v o 1/2v o t phl t dplh t dphl t skew = | t dplh - t dphl | +3v 0v 5v v ol a, b 0v 1.5v 1.5v t zl t zh v oh a, b 2.3v 2.3v t lz t hz 0.5v 0.5v output normally low output normally high mx or tx_enable v oh v ol receiver out (v oh - v ol )/2 (v oh - v ol )/2 t plh f > 10mhz; t r < 10ns; t f < 10ns output v 0d2 + v 0d2 ? a ? b 0v 0v t phl input t skew = | t phl - t plh |
17 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation figure 39. receiver enable and disable times figure 40. v.28 (rs-232) and v.10 (rs-423) driver enable and disable times +3v 0v 5v receiver out 0v 1.5v 1.5v t zl t zh f = 1mhz; t r < 10ns; t f < 10ns receiver out 1.5v 1.5v t lz t hz 0.5v 0.5v output normally low output normally high v il v ih decx rcvr enable +3v 0v tx_enable 1.5v 1.5v t zl f = 60khz; t r < 10ns; t f < 10ns t out t lz output low 0v +3v 0v v oh 1.5v 1.5v t zh f = 60khz; t r < 10ns; t f < 10ns t out t hz output high 0v tx_enable v ol 0.5v v oh - v ol 0.5v - v ol 0.5v -
18 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation figure 41. typical v.28 driver output waveform figure 42. typical v.10 driver output waveform figure 43. typical v.11 driver output waveform figure 44. typical v.35 driver output waveform figure 45. typical v.11 driver output waveform at 20mhz figure 46. typical v.35 driver output waveform at 20 mhz
19 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation figure 47. functio nal diagram txd sd(a) v35tgnd1 sd(b) sden v cc v dd c1- v ss c1+ + 5v (decoupling capacitor not shown) 1 f regulated charge pump SP509 txce tt(a) v35tgnd2 tt(b) tten st st(a) v35tgnd3 st(b) sten rd(a) rxd rden rd(b) r t(a) rxc r ten r t(b) txc(a) txc txcen txc(b) cs(a) cts csen cs(b) dm(a) dsr dmen dm(b) rrt(a) dcd_dte rrten rrt(b) tm tm tmen rts rs(a) rs(b) rsen dtr tr(a) tr(b) tren dcd_dce rrc(a) rrc(b) rrcen ll ll(a) llen c2- c2+ 1 f 1 f 1 f gnd d0 d1 d2 term-off d-latch v .10-gnd v .35 mode tx enable 51ohms 51ohms 124ohms v .35 driver termination network v .35 mode rx enable 51ohms 51ohms 124ohms receiver termination network v .11 mode rl rl(a) rlen ic ri icen v35rgnd loopback
20 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation the SP509 contains highly integrated serial transceivers that offer programmability between interface modes through software control. the SP509 offers the hardware interface modes for rs-232 (v.28), rs-449/v.36 (v.11 and v.10), eia-530 (v.11 and v.10), eia-530a (v.11 and v.10), v.35 (v.35 and v.28) and x.21(v.11). the interface mode selection is done via three control pins, which can be latched via microprocessor control. the SP509 has eight drivers, eight receivers, and sipex's patented on-board charge pump (5,306,954) that is ideally suited for wide area network connectivity and other multi-protocol applications. other features include digital and line loopback modes, individual enable/disable control lines for each driver and receiver, fail-safe when inputs are either open or shorted, individual termination resistor ground paths, separate driver and receiver ground outputs, enhanced esd protection on driver outputs and receiver inputs. theory of operation the SP509 device is made up of 1) the drivers, 2) the receivers, 3) a charge pump, 4) dte/dce switching algorithm, and 5) control logic. drivers the SP509 has eight enhanced independent drivers. control for the mode selection is done via a three- bit control word into d0, d1, and d2. the drivers are prearranged such that for each mode of operation, the relative position and functionality of the drivers are set up to accommodate the selected interface mode. as the mode of the drivers is changed, the electrical characteristics will change to support the required signal levels. the mode of each driver in the different interface modes that can be selected is shown in table 1 . there are four basic types of driver circuits itu-t-v.28 (rs-232), itu-t-v.10 (rs-423), itu-t-v.11 (rs-422), and ccitt-v.35. the v.28 (rs-232) drivers output single-ended signals with a minimum of +5v (with 3k ? & 2500pf loading), and can operate over 120kbps. since the SP509 uses a charge pump to generate the rs-232 output rails, the driver outputs will never exceed +10v. the v.28 driver architecture is similar to sipex's standard line of rs-232 transceivers. the rs-423 (v.10) drivers are also single-ended signals which produce open circuit v ol and v oh measurements of +4.0v to +6.0v. when terminated with a 450 ? load to ground, the driver output will not deviate more than 10% of the open circuit value. this is in compliance of the itu v.10 specification. the v.10 (rs-423) drivers are used in rs-449/v.36, eia-530, and eia-530a modes as category ii signals from each of their corresponding specifications. the v.10 drivers are guaranteed to transmit over 120kbps, but can operate at over 1mbps if necessary. the third type of drivers are v.11 (rs-422) differential drivers. due to the nature of differential signaling, the drivers are more immune to noise as opposed to single-ended transmission methods. the advantage is evident over high speeds and long transmission lines. the strength of the driver outputs can produce differential signals that can maintain + 2v differential output levels with a load of 100 ? . the signal levels and drive capability of these drivers allow the drivers to also support rs-485 requirements of +1.5v differential output levels with a 54 ? load. the strength allows the SP509 differential driver to drive over long cable lengths with minimal signal degradation. the v.11 drivers are used in rs-449, eia-530, eia-530a and v.36 modes as category i signals which are used for clock and data. sipex's new driver design over its predecessors allow the SP509 to operate over 40mbps for differential transmission. features
21 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation the fourth type of drivers are v.35 differential drivers. there are only three available on the SP509 for data and clock (txd, txce, and txc in dce mode). these drivers are current sources that drive loop current through a differential pair resulting in a 550mv differential voltage at the receiver. these drivers also incorporate fixed termination networks for each driver in order to set the v oh and v ol depending on load conditions. this termination network is basically a ? configuration consisting of two 51 ? resistors connected in series and a 124 ? resistor connected between the two 50 ? resistors and a v35tgnd output. each of the three drivers and its associated termination will have its own v35tgnd output for grounding convenience. filtering can be done on these pins to reduce common mode noise transmitted over the transmission line by connecting a capacitor to ground. the drivers also have separate enable pins which simplifies half-duplex configurations for some applications, especially programmable dte/dce. the enable pins will either enable or disable the output of the drivers according to the appropriate active logic illustrated on figure 47 . the enable pins have internal pull-up and pull- down devices, depending on the active polarity of the receiver, that enable the driver upon power- on if the enable lines are left floating. during disabled conditions, the driver outputs will be at a high impedance 3-state. the driver inputs are both ttl or cmos compatible. all driver inputs have an internal pull-up resistor so that the output will be at a defined state at logic low (??. unused driver inputs can be left floating. the internal pull-up resistor value is approximately 500k ? . receivers the SP509 has eight enhanced independent receivers. control for the mode selection is done via a three-bit control word that is the same as the driver control word. therefore, the modes for the drivers and receivers are identical in the application. like the drivers, the receivers are prearranged for the specific requirements of the synchronous serial interface. as the operating mode of the receivers is changed, the electrical characteristics will change to support the required serial interface protocols of the receivers. table 1 shows the mode of each receiver in the different interface modes that can be selected. there are two basic types of receiver circuits?tu-t-v .28 (rs-232) and itu-t-v.11, (rs-422). the rs-232 (v.28) receiver is single-ended and accepts rs-232 signals from the rs-232 driver. the rs-232 receiver has an operating input voltage range of +15v and can receive signals downs to +3v. the input sensitivity complies with rs-232 and v .28 at +3v. the input impedance is 3k ? to 7k ? in accordance to rs- 232 and v .28. the receiver output produces a ttl/cmos signal with a +2.4v minimum for a logic ??and a +0.4v maximum for a logic ?? the rs-232 (v.28) protocol uses these receivers for all data, clock and control signals. they are also used in v.35 mode for control line signals: cts, dsr, ll, and rl. the rs-232 receivers can operate over 120kbps. the second type of receiver is a differential type that can be configured internally to support itu-t-v.10 and ccitt-v.35 depending on its input conditions. this receiver has a typical input impedance of 10k ? and a differential threshold of less than +200mv, which complies with the itu-t-v.11 (rs-422) specifications. v.11 receivers are used in rs-449/v.36, eia-530, eia-530a and x.21 as category i signals for receiving clock, data, and some control line signals not covered by category ii v.10 circuits. the differential v.11 transceiver has improved architecture that allows over 40mbps transmission rates. receivers dedicated for data and clock (rxd, rxc, txc) incorporate internal termination for v.11. the termination resistor is typically 120 ? connected between the a and b inputs. the termination is essential for minimizing crosstalk and signal reflection over the transmission line . the minimum value is guaranteed to exceed 100 ? , thus complying with the v.11 and rs-422 specifications. this resistor is invoked when the receiver is operating as a v.11 receiver, in modes eia-530, eia-530a, rs-449/v.36, and x.21.
22 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation the same receivers also incorporate a termination network internally for v.35 applications. for v.35, the receiver input termination is a ? termination consisting of two 51 ? resistors connected in series and a 124 ? resistor connected between the two 50 ? resistors and v35rgnd output. the v35rgnd is usually grounded. the receiver itself is identical to the v.11 receiver. the differential receivers can be configured to be itu-t-v.10 single-ended receivers by internally connecting the non-inverting input to ground. this is internally done by default from the decoder. the non-inverting input is rerouted to v10gnd and can be grounded separately. the itu-t-v.10 receivers can operate over 1mbps and are used in rs-449/v.36, e1a-530, e1a-530a and x.21 modes as category ii signals as indicated by their corresponding specifications. all receivers include an enable/disable line for disabling the receiver output allowing convenient half-duplex configurations. the enable pins will either enable or disable the output of the receivers according to the appropriate active logic illustrated on figure 47 . the receiver? enable lines include an internal pull-up or pull-down device, depending on the active polarity of the receiver, that enables the receiver upon power up if the enable lines are left floating. during disabled conditions, the receiver outputs will be at a high impedance state. if the receiver is disabled any associated termination is also disconnected from the inputs. all receivers include a fail-safe feature that outputs a logic high when the receiver inputs are open, terminated but open, or shorted together. for single-ended v.28 and v.10 receivers, there are internal 5k ? pull-down resistors on the inputs which produces a logic high (?? at the receiver outputs. the differential receivers have a proprietary circuit that detect open or shorted inputs and if so, will produce a logic high (?? at the receiver output. charge pump the charge pump is a sipex -patented design (5,306,954) and uses a unique approach compared to older less-efficient designs. the charge pump still requires four external capacitors, but uses four-phase voltage shifting technique to attain symmetrical power supplies. the charge pump v dd and v ss outputs are regulated to +5.8v and -5.8v, respectively. there is a free-running oscillator that controls the four phases of the voltage shifting. a description of each phase follows. phase 1 __v ss charge storage during this phase of the clock cycle, the positive side of capacitors c 1 and c 2 are initially charged to v cc . c+ is then switched to ground and the charge in c 1 - is transferred to c 2 -. since c 2 + is connected to v cc , the voltage potential across capacitor c 2 is now 2 x v cc . phase 2 ? ss transfer ?hase two of the clock connects the negative terminal of c 2 to the v ss storage capacitor and the positive terminal of c 2 to ground, and transfers the negative generated voltage to c 3 . this generated voltage is regulated to ?.8v. simultaneously, the positive side of the capacitor c 1 is switched to v cc and the negative side is connected to ground. phase 3 ? dd charge storage ?he third phase of the clock is identical to the first phase?he charge transferred in c 1 produces ? cc in the negative terminal of c 1 which is applied to the negative side of the capacitor c 2 . since c 2 + is at v cc , the voltage potential across c 2 is 2 x v cc . phase 4 ? dd transfer ?he fourth phase of the clock connects the negative terminal of c 2 to ground, and transfers the generated 5.8v across c 2 to c 4 , the v dd storage capacitor. this voltage is regulated to +5.8v. at the regulated voltage, the internal oscillator is disabled and simultaneously with this, the positive side of capacitor c 1 is switched to v cc and the negative side is connected to ground, and the cycle begins again. the charge pump cycle will continue as long as the operational conditions for the internal oscillator are present.
23 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation since both v + and v - are separately generated from v cc ; in a no-load condition v + and v - will be symmetrical. older charge pump approaches that generate v - from v + will show a decrease in the magnitude of v - compared to v + due to the inherent inefficiencies in the design. the clock rate for the charge pump typically operates at 250khz. the external capacitors can be as low as 1 f with a 16v breakdown voltage rating. term_off function the SP509 contains a term_off pin that disables all three receiver input termination networks regardless of mode. this allows the device to be used in monitor mode applications typically found in networking test equipment. the term_off pin internally contains a pull-down device with an impedance of over 500k ? , which will default in a ?n?condition during power-up if v.35 receivers are used. the individual receiver enable line and the shutdown mode from the decoder will disable the termination regardless of term_off. loopback function the SP509 contains a loopback pin that invokes a loopback path. this loopback path is illustrated in figure 52 . loopback has an internal pull-up resistor that defaults to normal mode during power up or if the pin is left floating. during loopback, the driver output and receiver input characteristics will still adhere to its appropriate specifications. decoder and d_latch function the SP509 contains a d_latch pin that latches the data into the d0, d1, and d2 decoder inputs. if tied to a logic low (??, the latch is transparent, allowing the data at the decoder inputs to propagate through and program the SP509 accordingly. if tied to a logic high(??, the latch locks out the data and prevents the mode from changing until this pin is brought to a logic low. there are internal pull-up devices on d0, d1, and d2, which allow the device to be in shutdown mode (?11? upon power up. however , if the device is powered -up with the d_latch at a logic high, the decoder state of the SP509 will be undefined. esd tolerance the SP509 device incorporates ruggedized esd cells on all driver output and receiver input pins. the esd structure is improved over our previous family for more rugged applications and environments sensitive to electrostatic discharges and associated transients. ctr1/ctr2 european compliancy as with all of sipex? previous multi-protocol serial transceiver ic? the drivers and receivers have been designed to meet all the requirements to net1/net2 and tbr2 in order to meet ctr1/ctr2 compliancy. the SP509 is also tested in-house at sipex and adheres to all the net1/2 physical layer testing and the itu series v specifications before shipment. please note that although the SP509 , as with its predecessors, adhere to ctr1/ctr2 compliancy testing, any complex or unusual configuration should be double-checked to ensure ctr1/ctr2 compliance. consult the factory for details.
24 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation figure 48. SP509 loopback path sd(a) sd(b) rd(a) rd(b) tt(a) tt(b) r t(a) r t(b) txd rxd txce rxc st(a) st(b) txc(a) txc(b) st txc rs(a) rs(b) cs(a) cs(b) tr(a) tr(b) dm(a) dm(b) rts cts dtr dsr rrc(a) rrc(b) rrt(a) rrt(b) dcd_dce dcd_dte rl(a) ic rl ri ll(a) tm(a) ll tm
25 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation figure 49. configuring SP509 to operate as either dce or dte 1 f 1 f 1 f v cc v dd c1- c2- v ss c1+ c2+ 1 f SP509 txd txce st rts dtr dcd_dce rl rxc txc cts dsr dcd_dte ri tm 10 f 3 sden 10 llen 5 sten * - driver applies for dce only on pins 15 and 12. receiver applies for dte only on pins 15 and 12. vcc #103 #108 #105 #141 #105 #115 #106) #107 #109 bi-directional bus. input line output line #114 #113 #109 ll rxd 4 tten 6 rsen 7 tren 8 rrcen 9 rlen 11 rden 18 tmen 13 txcen 12 rten 14 csen 15 dmen 16 rrten 17 icen v10_gnd 58 v35tgnd1 99 v35tgnd2 94 35tgnd3 89 v35rgnd 46 term_off 22 latch 23 d0 19 d1 20 d2 21 logic section vcc #125 #142 #140 dce/dte driver applies for dce only on pins 8 and 10. receiver applies for dte only on pins 8 and 10. loopback 27 vcc 73 72 69 70 67 66 28 2 txd_rxd_a 97 sd(a) 100 s(b) 29 30 92 tt(a) 95 tt(b) 87 st(a) 90 st(b) 31 83 rs(a) 85 rs(b) 32 75 tr(a) 78 tr(b) 33 34 35 81 rrc(a) 79 rrc(b) 65 rl(a) 63 ll(a) #113 circuit # 14 txd_rxd_b 24 txce_txc_a 11 txce_txc_b 4r ts_cts_a 19 rts_cts_b 20 dtr_dsr_a 23 dtr_dsr_b 21 rl_ri 18 ll_tm + 36 37 38 39 40 41 42 43 25 ll_tm 62 tm 61 ic 59 rrt(b) 22 ri_rl 10 dcd-dcd-b 60 rrt(a) 8 dcd_dcd_a 22 dsr_dtr_b 13 cts_rts_b 12 txc_rxc_b 56 dm(b) 57 dm(a) 54 cs(b) 55 cs(a) 51 txc(b) 53 txc(a) 49 rt(b) 50 rt(a) 47 rd(b) 48 rd(a) 6 dsr_dtr_a 5 cts_rts_a 15 txc_rxc_a 9 rxc_txce_b 17 rxc_txce_a 16 rxd_txd_b 3 rxd_txd_a serial port connector pins
26 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation package: 100 pin lqfp 100 pin lqfp pin 1 e1 d1 d c l b e seating plane a1 c l e a l 11 -13 0 min 0 ?7 0.2 rad max. 0.08 rad min. dimensions minimum/maximum (mm) symbol a a1 a2 b d d1 e e e1 n 100?pin lqfp jedec ms-026 (bed) variation min nom max 1.60 0.05 0.15 1.35 1.40 1.45 0.17 0.22 0.27 16.00 bsc 14.00 bsc 0.50 bsc 16.00 bsc 14.00 bsc 100 a c l1 a2 11 -13 common dimensions symbl min nom max c 0.09 0.20 l 0.45 0.60 0.75 l1 1.00 ref
27 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation dce configuration date: 6/14/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation 27 recommended signals and port pin assignments pin number pin mnemonic circuit pin mnemonic pin number signal type mnemo nic db-25 pin(f) signal type mnemo nic db-25 pin(f) signal type mnemo nic db-37 pin(f) signal type mnemo nic m34 pin(f) signal type mnemo nic db-15 pin(f) 28 txd sd(a) 97 v.28 bb 3 v.11 bb(a) 3 v.11 rd(a) 6 v.35 104 r v.11 r(a) 4 3 sden sd(b) 100 v.11 bb(b) 16 v.11 rd(b) 24 v.35 104 t v.11 r(b) 11 29 txce tt(a) 92 v.28 dd 17 v.11 dd(a) 17 v.11 rt(a) 8 v.35 115 v v.11 b(a) 7** 4 tten tt(b) 95 v.11 dd(b) 9 v.11 rt(b) 26 v.35 115 x v.11 b(b) 14** 30 st st(a) 87 v.28 db 15 v.11 db(a) 15 v.11 st(a) 5 v.35 114 y v.11 s(a) 6 5 sten st(b) 90 v.11 db(b) 12 v.11 st(b) 23 v.35 114 aa v.11 s(b) 13 31 rts rs(a) 83 v.28 cb 5 v.11 cb(a) 5 v.11 cs(a) 9 v.28 106 d v.11 i(a) 5 6 rsen rs(b) 85 v.11 cb(b) 13 v.11 cs(b) 27 v.11 i(b) 12 32 dtr tr(a) 75 v.28 cc 6 v.11 cc(a) 6 v.11 dm(a) 11 v.28 107 e 7 tren tr(b) 78 v.11 cc(b) 22 v.11 dm(b) 29 33 dcd_dce rrc(a) 81 v.28 cf 8 v.11 cf(a) 8 v.11 rr(a) 13 v.28 109 f 8 rrcen rrc(b) 79 v.11 cf(b) 10 v.11 rr(b) 31 34 rl rl(a) 65 v.28 ce 22 v.28 125 j 9 rlen 35 ll ll(a) 63 v.28 tm 25 v.10 tm 25 v.10 tm 18 v.28 142 nn 10 llen# 36 rxd rd(a) 48 v.28 ba 2 v.11 ba(a) 2 v.11 sd(a) 4 v.35 103 p v.11 t(a) 2 11 rden# rd(b) 47 v.11 ba(b) 12 v.11 sd(b) 22 v.35 103 s v.11 t(b) 9 37 rxc rt(a) 50 v.28 da 24 v.11 da(a) 24 v.11 tt(a) 17 v.35 113 u v.11 x(a) 7** 12 rten# rt(b) 49 v.11 da(b) 11 v.11 tt(b) 35 v.35 113 w v.11 x(b) 14** 38 txc txc(a) 53 13 txcen# txc(b) 51 39 cts cs(a) 55 v.28 ca 4 v.11 ca(a) 4 v.11 rs(a) 7 v.28 105 c v.11 c(a) 3 14 csen# cs(b) 54 v.11 ca(b) 19 v.11 rs(b) 25 v.11 c(b) 10 40 dsr dm(a) 57 v.28 cd 20 v.11 cd(a) 20 v.11 tr(a) 12 v.28 108 h 15 dmen# dm(b) 56 v.11 cd(b) 23 v.11 tr(b) 30 41 dcd_dte rrt(a) 60 16 rrten# rrt(b) 59 42 ri ic 61 v.28 rl 21 v.10 rl 21 v.10 rl 14 v.28 140 n 17 icen# 43 tm tm(a) 62 v.28 ll 18 v.10 ll 18 v.10 ll 10 v.28 141 l 18 tmen spare drivers and receivers may be used for optional signals (signal quality, rate detect, standby) or may be disabled using individual enable pins for each driver and receiver ** x.21 use either b() or x(), not both pin assignments and signal functions are subject to national or regional variation and proprietary / non-standard implementations receiver_7 receiver_8 rs-449 v.35 x.21 driver_1 rs-232 or v.24 eia-530 receiver_5 receiver_6 driver_7 driver_8 receiver_2 receiver_3 receiver_1 sp508 multiprotocol configured as dce interface to system logic interface to port- connector receiver_4 driver_2 driver_3 driver_4 driver_5 driver_6
28 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation dte configuration date: 6/14/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation 28 recommended signals and port pin assignments pin number pin mnemonic circuit pin mnemonic pin number signal type mnemo nic db-25 pin(m) signal type mnemo nic db-25 pin(m) signal type mnemo nic db-37 pin(m) signal type mnemo nic m34 pin(m) signal type mnemo nic db-15 pin(m) signal type mnemo nic din-8 pin(f) 28 txd sd(a) 97 v.28 ba 2 v.11 ba(a) 2 v.11 sd(a) 4 v.35 103 p v.11 t(a) 2 v.11 txd - 3 3 sden sd(b) 100 v.11 ba(b) 14 v.11 sd(b) 22 v.35 103 s v.11 t(b) 9 v.11 txd + 6 29 txce tt(a) 92 v.28 da 24 v.11 da(a) 24 v.11 tt(a) 17 v.35 113 u v.11 x(a) 7** 4 tten tt(b) 95 v.11 da(b) 11 v.11 tt(b) 35 v.35 113 w v.11 x(b) 14** 30 st st(a) 87 5 sten st(b) 90 31 rts rs(a) 83 v.28 ca 4 v.11 ca(a) 4 v.11 rs(a) 7 v.28 105 c v.11 c(a) 3 6 rsen rs(b) 85 v.11 ca(b) 19 v.11 rs(b) 25 v.11 c(b) 10 32 dtr tr(a) 75 v.28 cd 20 v.11/10 cd(a) 20 v.11 tr(a) 12 v.28 108 h v.10 hsko 1 7 tren tr(b) 78 v.11/z cd(b) 23 v.11 tr(b) 30 33 dcd_dce rrc(a) 81 8 rrcen rrc(b) 79 34 rl rl(a) 65 v.28 rl 21 v.10 rl 21 v.10 rl 14 v.28 140 n 9 rlen 35 ll ll(a) 63 v.28 ll 18 v.10 ll 18 v.10 ll 10 v.28 141 l 10 llen# 36 rxd rd(a) 48 v.28 bb 3 v.11 bb(a) 3 v.11 rd(a) 6 v.35 104 r v.11 r(a) 4 v.11 rxd- 5 11 rden# rd(b) 47 v.11 bb(b) 16 v.11 rd(b) 24 v.35 104 t v.11 r(b) 11 v.11 rxd+ 8 37 rxc rt(a) 50 v.28 dd 17 v.11 dd(a) 17 v.11 rt(a) 8 v.35 115 v 12 rten# rt(b) 49 v.11 dd(b) 9 v.11 rt(b) 26 v.35 115 x 38 txc txc(a) 53 v.28 db 15 v.11 db(a) 15 v.11 st(a) 5 v.35 114 y v.11 s(a) 6 13 txcen# txc(b) 51 v.11 db(b) 12 v.11 st(b) 23 v.35 114 aa v.11 s(b) 13 39 cts cs(a) 55 v.28 cb 5 v.11 cb(a) 5 v.11 cs(a) 9 v.28 106 d v.11 i(a) 5 gnd 14 csen# cs(b) 54 v.11 cb(b) 13 v.11 cs(b) 27 v.11 i(b) 12 v.10* hski 2 40 dsr dm(a) 57 v.28 cc 6 v.11/10 cc(a) 6 v.11 dm(a) 11 v.28 107 e v.11 b(a) 7** v.10 gpi 7 15 dmen# dm(b) 56 v.11/z cc(b) 22 ? v.11 dm(b) 29 v.11 b(b) 14** 41 dcd_dte rrt(a) 60 v.28 cf 8 v.11 cf(a) 8 v.11 rr(a) 13 v.28 109 f 16 rrten# rrt(b) 59 v.11 cf(b) 10 v.11 rr(b) 31 42 ri ic 61 v.28 ce 22 v.10 ri 22 ? v.28 125 j 17 icen# 43 tm tm(a) 62 v.28 tm 25 v.10 tm 25 v.10 tm 18 v.28 142 nn 18 tmen rs-449 v.35 x.21 receiver_7 driver_3 driver_4 driver_5 eia-530 receiver_4 receiver_5 receiver_6 driver_7 driver_8 driver_6 driver_2 sp508 multiprotocol configured as dte interface to system logic interface to port- connector driver_1 ? eia-530 uses v.11 (differential) for dsr (cc) and dtr (cd) signals; eia-530-a uses single- ended v.10 for dsr and dtr and adds ri signal on pin 22 appletalk? spare drivers and receivers may be used for optional signals (signal quality, rate detect, standby) or may be disabled using individual enable pins for each driver and receiver ** x.21 use either b() or x(), not both pin assignments and signal functions are subject to national or regional variation and proprietary / non-standard implementations receiver_1 receiver_2 receiver_3 receiver_8 rs-232 or v.24
29 date: 8/19/04 SP509 enhanced wan multi?protocol serial transceiver ? copyright 2004 sipex corporation ordering information model temperature range package types SP509cf ............................................... 0 c to +70 c ............................................................ 100 lead lqfp corporation analog excellence sipex corporation reserves the right to make changes to any products described herein. sipex does not assume any liability aris ing out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor t he rights of others. sipex corporation headquarters and sales office 233 south hillview drive milpitas, ca 95035 tel: (408) 934-7500 fax: (408) 935-7600 date revision description 3/31/04 a implemented tracking revision. 6/14/04 b added tables to pages 27 and 28. 8/19/04 c corrected pin description table and figure 49. updated dce/dte tables. revision history available in lead free packaging. to order add ?-l? suffix to part number. example: SP509cf/tr = standard; SP509cf-l/tr = lead free

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